The present invention relates to the fabrication of semiconductor integrated circuits, and more specifically to an apparatus and method of making a strained channel field effect transistor (FETs) such as an insulated gate field effect transistor (IGFET) in which a stress is applied to the channel region by a semiconductor alloy material disposed adjacent the channel region.
Both theoretical and empirical studies have demonstrated that carrier mobility in a transistor can be greatly increased when a stress of sufficient magnitude is applied to the channel region of a transistor to create a strain therein. Stress is defined as force per unit area. Strain is a dimensionless quantity defined as the change in the dimension of an item, e.g., a change in its length, versus the original dimension, e.g., the original length, when a force is applied in the same direction, i.e., in the direction of its length, in this case. Thus, strain can be either tensile or compressive. In p-type field effect transistors (PFETs), a compressive stress applied to the channel region in the direction of its length, i.e., a compressive longitudinal stress, creates a strain which is known to increase the drive current of the PFET.
Commonly assigned, co-pending U.S. patent application Ser. No. 10/604,607 filed Aug. 4, 2003 and U.S. patent application Ser. No. 10/605,134 filed Sep. 10, 2003 describe ways of applying stresses to the channel regions of FETs to increase their drive current. These applications are hereby incorporated by reference herein in their entirety. As described therein, one way of applying stress to the channel region of a FET is to form shallow regions of a semiconductor alloy material adjacent the channel region, the semiconductor alloy material being lattice-mismatched to the semiconductor material that exists in the channel region. Thus, in one example, shallow regions of single-crystal silicon germanium (SiGe) are formed on opposite sides of a channel region that is provided in a region of silicon. As also described in the incorporated applications, the SiGe regions are disposed in areas of the substrate that coincide with implants which define the source and drain regions of the FET.
However, it is not always desirable for the SiGe regions of a strained channel transistor structure to coincide with the locations of the source and drain implants. While the SiGe regions need to be placed close to the channel region to apply the stress needed to obtain high drive current, placed them too close can cause problems such as causing the threshold voltage of the transistor to deviate from a desired value.
In addition, the source and drain regions of a FET are desirably spaced close to each other to increase the drive current iD of the FET by making the length (L) of the channel region small. This follows from the equationiD=f(W/L)
where iD is the drive current of the transistor, W is the width, and L is the length of the channel region, i.e., the spacing between the source and drain regions of the substrate. However, there is a limit to how close the source and drain regions can be placed to each other. If they are placed too close to each other, short channel effects occur, which could cause difficulty in turning off the transistor. When the transistor cannot be fully turned off, excessive leakage current is produced when the transistor is off, causing more power to be consumed even when the transistor is off. Excessive leakage current can also sometimes cause output signal levels to drift undesirably.
For the above reasons, it would be desirable to provide a structure and method of forming a FET in which semiconductor alloy regions are formed at a spacing from the channel region, the spacing being selected independently from the locations at which the edges of the source and drain regions are placed.